Adder logic to perform integer addition is a basic building block of microprocessor design-adders are central to ALU design, but have numerous other uses such as address calculations and program counter incrementing. Optimizing the speed of addition operations commonly involves implementing in place of a simple carry-ripple adder one of three adder designs: carry lookahead, carry-select, or carry-skip.
Without limiting the scope of the invention, this background information is provided in the context of a specific problem to which the invention has application: for use in a microprocessor, a carry-skip adder design in which addition operations do not require precharging to clear the carry-in inputs, allowing adder operations to be completed in a single clock cycle.
The operation of a carry-skip adder is described in Section 1 of the Detailed Description. Basically, this type of adder is formed by a number of carry-ripple blocks, each receiving as inputs a plurality of addend/augend bits to be summed along with a carry-in, and performing a full-ripple carry addition to provide (a) corresponding sum outputs with a ripple carry-out, as well as (b) an associated propagate value. An addition operation is accomplished in two stages: (a) in the first stage, each carry-ripple block performs a full ripple carry addition with an associated carry-skip operation to set up the carry-in inputs for each block after the first, and (b) in the second stage, each block performs a second full ripple carry addition with the carry-in inputs to obtain the final sum.
Proper operation of a carry-skip adder requires that prior to performing the first stage full ripple carry addition, all carry-in inputs to each stage must be cleared. Otherwise, under certain boundary conditions, the carry-skip operation will be negated, and the adder will revert to full carry-ripple operation (with the attendant performance degradation).
One common way to ensure that the carry-in inputs are initially cleared is to precharge the inputs to the adder. However, precharging is disadvantageous in that it prevents the addition operation from being performed in a single CPU clock cycle. That is, if the adder inputs are precharged during a first clock phase, then both stages of the carry-skip addition operation cannot be completed in the second clock phase.
Accordingly, a specific object of the invention is to provide an improved carry-skip adder design that does not rely on precharging to clear the carry-in inputs, thereby permitting an addition operation to be completed in one clock cycle.